With the increasing scope of functionality of electronic systems and advances in miniaturization, traditional chip designs are coming ever closer to their technological and economic limits. Through novel integration concepts – such as chip stacking or the use of interposers – it is possible to achieve higher data throughput while simultaneously lowering energy consumption and reducing space requirements. Modern packaging solutions up to chiplets also enable the integration of diverse component types, such as processors, sensors and wireless interfaces, in a single module.
Particular challenges in the design process include mastering complexity, optimal utilization of the additional degrees of freedom and consideration of the close thermal, mechanical and electrical coupling in the stacked system. Fraunhofer IIS/EAS can assist you in solving these challenges for an optimized system packaging.