Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems
Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems

Research Topics

System Packaging

substrate for system on chip
Fine-pitch package substrate for a multifunctional system on chip
Electronics solutions based on chiplets are the first to allow the integration of various functional units in different technologies on a substrate or into a 3D chip structure
© Fraunhofer IIS
Electronics solutions based on chiplets are the first to allow the integration of various functional units in different technologies on a substrate or into a 3D chip structure

With the increasing scope of functionality of electronic systems and advances in miniaturization, traditional chip designs are coming ever closer to their technological and economic limits. Through novel integration concepts – such as chip stacking or the use of interposers – it is possible to achieve higher data throughput while simultaneously lowering energy consumption and reducing space requirements. Modern packaging solutions up to chiplets also enable the integration of diverse component types, such as processors, sensors and wireless interfaces, in a single module.

Particular challenges in the design process include mastering complexity, optimal utilization of the additional degrees of freedom and consideration of the close thermal, mechanical and electrical coupling in the stacked system. Fraunhofer IIS/EAS can assist you in solving these challenges for an optimized system packaging.

The Chiplet Center of Excellence

Together with Fraunhofer IZM and Fraunhofer ENAS, we have launched a pioneering research initiative: the Chiplet Center of Excellence (CCoE). Together with industry, we drive forward the introduction of chiplet technologies.

Robust chiplet solutions

The innovative chiplet approach offers great potential for the automotive and industrial sectors. The modular principle behind chiplets enables efficient design and production: individual components have to be produced only once and can then be flexibly combined to create tailored solutions.

By integrating various functional units, chiplet technology enhances performance through the opportunity to involve mixed processing nodes from major nodes down to 5nm, as well as more specific technologies such as SiGe and GaN. This offers major advantages when it comes to the cost-effective production of high-performance specialized chips.

Fraunhofer IIS is researching specialized chiplet solutions that meet the requirements for long-term stability and reliability. Particularly with regard to chiplet architectures and design, Fraunhofer IIS supports you in utilizing the advantages of the chiplet approach from concept to prototype realization.

Our Services

We accompany and support you in your modern packaging technology projects from the conception to the prototype. We offer you:

System packaging
© Katharina Knaut
System packaging
  • Consulting on currently available solutions for high levels of integration
  • Conducting of preliminary studies to assess system performance and costs
  • Selection of the best integration technology (e.g. interposers based on Fraunhofer technology) according to customer requirements and application conditions
  • Support from the design to prototype manufacturing and all the way to series production
  • Simulation of thermal, electrical and mechanical effects for complex packages
  • Assembly Design Kit (ADK) for verification to ensure that a package meets manufacturability and performance requirements
  • Planning and organizing the prototype production at our partners
 

Contact us for an individual offer.

Added Value for You

Our years of experience in system integration as well as our extensive network make us a valuable partner in the customer-specific design of integration solutions.

  • Higher system performance combined with low energy consumption
  • Maximum miniaturization of complex systems, such as sensor systems
  • Cost savings compared with comparable ASIC implementation, in particular for small quantities
  • Manufacturer-independent evaluation of available integration solutions
  • Reduced risk in the introduction of new packaging solutions
  • On-time implementation of prototypes and small series
  • Central point of contact from conception to design and prototype manufacturing

Get a closer look at our work

References

Industrial Reference

Dream Chip
Technologies GmbH

Fine-pitch package substrate for a multifunctional system-on-chip

Customer Reference DreamChip

Reference Project

SiPoB 3-D

The scientists at Fraunhofer IIS/EAS are working in this project on design methods and design flows for the so-called system-package-board co-design. This method should accelerate the development of complex systems-in-package.

 

Information Material

Reference Project

Memory³

Fraunhofer IIS/EAS pursued within the project an especially small and energy-efficient microchip layout for cost efficient and high-performance cameras.

Reference Project

ESiMED

ESiMED seeked to simplify access to technologies like system-in-package (SiP) for companies from the medical technology sector.