News

 

Meet us at the Embedded World Trade Fair

Under the theme "Embedded. Responsible. Sustainable." the Embedded World Exhibition & Conference will take place in Nuremberg in March. We will be present in hall 4 at booth 4-422 and are looking forward to your visit.

 

Press Release / Nov. 10, 2022

Chiplet Project in 5 nm Process Technology from Samsung

Fraunhofer IIS/EAS has announced today their first implementation of the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung’s 5 nm technology. This work represents a first step towards supporting the rapid introduction of chiplet technology, even enabling electronic products with smaller production runs.

 

Press Release / Aug. 18, 2022

Silicon Measurements for International Collaboration Project

Fraunhofer IIS/EAS performed silicon measurements and lab testing for a design that Cadence Design Systems, Inc. and GlobalFoundries collaborated on to accelerate 5G and mobile design innovation. As a proof point, the Cadence full-flow RF solution was used to design and tape out a 28GHz 5G mmWave IC as a complete system-in-package (SiP) solution.

 

Webinar: Reusable Analog-IP on Feb 15, 2023

In this webinar, we will show solutions to help analog/mixed-signal IC designers with efficiency as well as risk management using design concepts and automated design tools. The webinar language is English.

Fraunhofer Institute for Integrated Circuits IIS

Division Engineering of Adaptive Systems EAS

Muenchner Strasse 16
01187 Dresden, Germany
Phone +49 351 45691-0
Contact



 

From our work

System Packaging

With the increasing scope of functionality of electronic systems and advances in miniaturization, traditional chip designs are coming ever closer to their technological and economic limits. That is why novel integration concepts are needed.

 

 

Among others, our offers will help you profit from:

  • Higher system performance combined with low energy consumption
  • Maximum miniaturization of complex systems
  • Cost savings compared with comparable ASIC implementation
  • Reduced risk in the introduction of new packaging solutions

Research Fab Microelectronics

Fraunhofer IIS/EAS is participant of the Research Fab Microelectronics Germany.

 

Logo Research Fab Microelectronics