3D designs for systems-in-package (SiP) often incorporate various modern technologies such as through-silicon-vias (TSV), through-encapsulant-vias (TEV), redistribution layers (RDL) and micro-bumps. Additional components are also integrated into the board that make the entire system more complex. Because the prototypes for such systems are very expensive, extensive simulations are required before production. However, the typical design and simulation environments cannot take all components of the system into account simultaneously. In addition, no company is currently capable of successfully developing a complete system-in-package on its own. An integrated chip-package-board-co-design environment shall be created.
The new design environment must encompass semiconductor chips, passive components, the housing and the board. Only this way is it possible to ideally combine these components into an integral system. An optimal compromise between technology and costs is required. In order to achieve this, Fraunhofer IIS/EAS is working with partners on the creation of a uniform development environment for electronic design that encompasses the data exchange between the domains of chip, package and board.
In addition, a flexible approach should be taken to the coordination between design and simulation environments, even when the partners participating in the system development are using different software tools. To master the great diversity of technologies, tools are required that support the optimal selection of technologies, components, assembly and packaging variants. Corresponding development blocks are being developed that can be utilized in the later design. Simulation models that function precisely and efficiently at their particular level of extraction are also under development. This significantly improves the quality of a simulation and helps reduce expensive hardware prototypes considerably.