Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EASILIAS
Project Goals
In contrast to digital system components, the conditions affecting analog circuits are far more complex. For this reason, they are even today still largely designed by hand all the way down to the layout. This makes the design process very labor intensive. It can even significantly exceed the labor required for design of the often more extensive digital portion since that design process is automated.
The goal of the project partners is therefore to develop new methods and tools for analog layout design that significantly simplify the processes for producing the first functioning layout. High reusability and reliability of the created circuits – including in various technologies – should also be guaranteed.
Approach
As part of this project, an intelligent library with universal, configurable circuit blocks will be developed that can be used to assemble hierarchically more complex circuits. This is based on the methods of one partner for generic layout description. With this method, it is possible to specify circuits, layouts and test programs in a uniform format and quickly produce variants of a circuit for different target parameters and technologies.
With the help of optimization processes, these predefined circuit blocks (called analog IPs) can then be adapted to the respective requirements of the complete circuit. A selection of typical design components will also be offered for a variety of applications and for various complex systems. This will support developers particularly during the layout process and eliminate much routine work.
