Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS
Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS

Research Topics

© Fraunhofer IIS/EAS, Foto: Jürgen Lösel

Functional Safety

System design and verification tools
© Jürgen Lösel

System design and verification tools

New areas of application for electronics demand not only higher performance and energy efficiency; they also call for better reliability and robustness on the part of the individual components. However, the variety of possible error sources rises with the increasing complexity, especially in programmable systems. This forces developers to verify the functional reliability of their design at various abstraction levels and to implement requirements according to standards such as IEC EN 61508 and ISO 26262.

Thanks to our many years of experience in the area of system development and verification, we offer you tools and services for the comprehensive ensuring of your safe design. Our practically proven methods allow you to combine high technical requirements withyour design and verification process.

Our Services

We advise and support you in research and industry projects with optimization of the functional reliability of your design processes and verification of your design:

  • System modeling corresponding to customer specification
  • Provision and development of model libraries
  • Fault modeling and injection
  • Verification at RTL and system level based on current methods such as UVM SystemC
  • Development of customer-specific design flows and interfaces
  • Consulting in the area of system development and verification
  • Trainings in SystemC / SystemC AMS
 

 

§  Verifikation auf RTL und Systemlevel mittels neuster Methoden wie z.B. UVM

§  Entwicklung kundenspezifischer Designflows und Interfaces

Added Value for You

With our expert knowledge in system development and verification, we help you to thoroughly safeguard complex systems while offering the following advantages:

Hardware-in-the-loop with SystemC

Hardware-in-the-loop with SystemC

  • Close interweaving of ESL modeling, fault injection and HiL simulation
  • Comprehensive requirement management and tracking
  • Integrated verification of functional safety requirements
  • Shorter turn-around times in system development
  • Safeguarding of systems according to qualification requirements

References and More Information

Customer Reference

Elmos Semiconductor

Reduction of the verification workload for current and future IC design projects

Customer reference Elmos

Customer Reference

Verification Works

Optimization of a Design and Verification Workflow

Customer reference verification
 

© Alexandr Mitiuc - Fotolia

Information Material

Reference Project

VeTeSS

The project partners are striving to create new processes by which safety systems can be efficiently developed in compliance with ISO standard 26262.

Reference Project

Verdi

With today's design methods, the analog-digital barriers represent a major hurdle for evaluating the function of the entire system. VERDI developed a forward-looking design process that solves this problem.

Reference Project

ResCar

The objective of ResCar 2.0 was to develop a procedure by which the resilience and reliability of new electronic vehicle components can be taken into consideration already during the design phase.

Weitere Referenzen und interessante Links