Research Topics

System Integration

There are several technological variants regarding the placement of multiple dies as a system-in-package up to stacking them as 3D systems. Short conductor lengths in the system increase performance and reduce energy consumption. Die stacking also allows the integration of different components such as processors, sensors and wireless interfaces in a block. The path of the planar integrated circuit to the third dimension is tracked by the world's leading manufacturers in order to achieve the ambitious goals according to "More than Moore" in terms of features, density and cost.

Particular challenges in the design are the mastery of complexity, the optimal utilization of the additional degrees of freedom and consideration of the close thermal, mechanical and electrical coupling in the stacked system.

In this regard we develop tools, models, simulation methods and optimization techniques used to implement innovative solutions. To do this, we combine state-of-the-art tools for in-the-loop optimization across several physical domains and in all 3 dimensions and combine the extraordinary details of FEM models with the simulation speed of compact models.

Variety of Technologies for Integration of Multiple Dies Within a Package


  • Placement of different IC at package substrate
  • Wire bond or flip-chip connection
  • Integration of passive devices

interposer-based integration

  • Higher integration level using thinned silicon interposers
  • Signal routing between dies within the metal layers of interposers and its TSV

direct stacking

  • Highest integration density
  • Extremely short interconnects
  • Requires die and stack co-design

Our Services

Tire pressure sensor
© Photo Infineon Technologies AG

Tire pressure sensor

We accompany and support you in your projects about advanced packaging technologies from its conception up to the prototype. We offer you:

  • Selection of application-specific integration technology
  • Design assistance from concept to implementation
  • Studies to estimate cost and performance
  • Interposer design
  • 3D floorplanning
  • Modeling multi-physical effects (e.g., heat dissipation)
  • Planning and organizing the prototype production at our partners

Project Example: Memory³

In the project Memory³, Fraunhofer IIS/EAS' researchers develop a 3D microchip packaging for 4K high-performance video cameras. They place the processor and the memory chip on one layer (interposer) in the same package.

Compared to conventional chips, this solution has numerous advantages from high miniaturization, short connections and an effective heat-removal. By that data rates of up to 400 Gbit/s shall be achieved.

Memory³ chip design for very high rates in data transmission

Memory³ chip design for very high rates in data transmission

Heat removal in Memory³ chip

Heat removal in Memory³ chip

Wireless ECG Sensor in SiP Technology

The video shows the animation of a wireless ECG sensor, which was developed with our support, in size comparison.

Benefits for Our Customers

System-in-package chip

System-in-package chip

  • Higher performance and reduced energy consumption
  • Size and cost advantages with enhanced functionality
  • Reduced risk when introducing 3D integration technologies due to the Fraunhofer team's more than 10 years of experience.
  • Central point of contact starting from the system design, the design up to prototype production at our partners


We have developed our know-how in the following projects, for example

  • ESiMED: The project seeks to simplify access to the system-in-package technology for medical engineering.
  • Memory³: The partners are pursuing an especially small and energy-efficient microchip layout for inexpensive and high-performance 4K cameras
  • 3DIM3 (completed project): The European partners developed approaches for 3D-TSV technology (TSV = Through Silicon Via) in particular to allow this innovative technology to be employed effectively.
  • eBrains (completed project): e-BRAINS partners developed innovative applications for all aspects of life based on nanoscale sensor systems.
  • NEEDS (completed project): The partners worked on new design methods to optimize 3D chips with regard to costs and performance even before manufacturing .