© MEV-Verlag, Germany
Wo bin ich?
Learn how our solution on analog automation can support your IC design flow to meet tapeouts in time. Whether your design phase is to be accelerated, design migration eased, or your recurring tasks to be automated – with intelligent IPs, Fraunhofer IIS/EAS offers an applied solution for a new era of analog integrated circuit design with shorter development times for analog / mixed-signal products.
Participation in our webinars is always free of charge. We use the platform "Webex" for the realization of this offer. After your registration for this webinar topic, you will receive an invitation by e-mail in time before the event. In this invitation you will find a link to a registration screen, on which you only need to enter your e-mail address for authentication and then can participate in the webinar session.
We save your personal data, which you enter in this form, exclusively for the processing of your inquiry concerning this event. Further information on data protection at Fraunhofer IIS/EAS are to be found here.
Zur Webinar-Übersicht des Fraunhofer-Institutsteils EAS