UVM-SystemC language and class library presented at the North American SystemC User Group meeting co-located with the Design Automation Conference (DAC) on June 2, 2014.

The partners in the European research project “Verification for heterogeneous Reliable Design and Integration” (VERDI) are pleased to provide the Universal Verification Methodology (UVM) class library developed in the SystemC/C++ language to the Accellera Systems Initiative for further industry standardization and adoption.

UVM-SystemC is the result of a three year collaboration to develop a system-level verification methodology to make integrated circuits and embedded systems more reliable and their development more effective. The project is funded by the European Union's Seventh Framework Programme (FP7).

The Accellera Systems Initiative drives the UVM standardization and creation of the reference implementation based on IEEE Std. 1800™-2012 (Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language). The UVM-SystemC implementation is based on IEEE Std. 1666™-2011 (Standard SystemC Language Reference Manual), which will make the verification methodology more language agnostic and thus truly universal. Various Accellera working groups, such as the SystemC verification working group as well as the multi-language verification working group, already expressed their interest in this development and welcome the donation of UVM-SystemC.

Unlike other initiatives to create UVM in SystemC, the proof-of-concept class library developed in the VERDI project uses identical constructs as defined in the UVM (SystemVerilog) standard for test and sequence creation, verification component and test bench configuration, and execution by means of simulation. This will facilitate a seamless introduction of UVM-SystemC for users familiar with either SystemC or UVM. The proof-of-concept implementation has been documented in a language reference manual, which describes all language constructs and semantics of the UVM-SystemC library.

“The donation of this UVM-SystemC class library to Accellera is a logical next step to further advance this system-level verification methodology for industry wide usage,” said Karsten Einwich, VERDI project leader working at Fraunhofer IIS/EAS. “I would like to thank all partners in this project, NXP, Infineon, Continental, Magillem, and University Pierre and Marie Curie, which all contributed to the realization of UVM in SystemC, and the European Commission for funding this project.”

The UVM-SystemC class library will be presented at the 20th North American SystemC User Group (NASCUG) meeting, which is co-located with the Design Automation Conference (DAC) on June 2, 2014. In a keynote speech held by Karsten Einwich, the concepts of UVM-SystemC are presented and it will be shown how they can be applied to real-world designs from the digital and mixed-signal domains.